1. Field of the Invention
The present invention deals with a method suitable for making microwave monolithic integrated circuits which each include at least one integrated bipolar planar transistor, i.e., may also contain further integrated components, such as insulated-gate field-effect transistors, integrated capacitors or integrated resistors.
2. Description of the Prior Art
For a better understanding and to simplify the description, however, the method in accordance with the invention and the discussion of the prior art will be illustrated in connection with a method of making a monolithic integrated circuit comprising at least one bipolar planar transistor. Accordingly, the illustrated embodiment is not to be read as as limitation, especially since it well known to fabricate monolithic integrated circuits on a common semiconductor wafer, to separate the individual circuit chips, and to finally package them singly.
A method of this type is described in the published West German applications DE-A 32 43 059 and DE-A 31 29 539. There doped polycrystalline silicon layers are used to form the base contact region, with its base electrode, and to form the emitter region, with its emitter electrode, in close proximity to each other in a self-aligned structure. With that method, a very low base lead resistance and a relatively high operating speed are achieved. In addition, such a self-aligned process has the advantage of permitting clearances during the photolithographic processes to be minimized, so that the lateral dimensions of the bipolar planar transistors are reduced.
A disadvantage of the method disclosed in the above-mentioned DE-A 31 29 539 lies in the fact that a complicated epitaxial process is used, which keeps the yield small. The method disclosed in the above-mentioned DE-A 32 43 059 suffers from the drawback that the overlap capacitance between the emitter electrode and the base electrode limits the operating speed.
The invention starts from the method disclosed in EP-A-71 665, which essentially overcomes the above disadvantages, and takes up the idea of DE-A 31 29 539 to provide the bulk resistors of the polycrystalline silicon electrodes, which pass into interconnecting paths, with superficial silicide layers in order to reduce the lead resistances. This, too, results in an increase in the operating speed of the monolithic integrated circuit.
While the above-mentioned West German published applications do not deal with the formation of the collector electrode, in one embodiment of the method disclosed in EP-A-71 665, the collector contact region, the emitter region and the base contact region are formed using self-aligning technology, but this does not apply to the formation of contacts to various regions.
In the method disclosed in the above-mentioned EP-A-71 665 for making a monolithic integrated circuit comprising at least one bipolar planar transistor, the collector region of the latter, which lies at a main surface of a wafer-shaped semiconductor substrate, forms a collector area at said surface side within the opening of a field-oxide layer. To form the emitter region, the base region, and the collector contact region using using self-aligning technology, the emitter area is covered with a portion of an oxidation mask layer of such a thickness that this layer is penetrated by dopants of the base region in an ion-implantation process of relatively high energy, and masked against dopants of the base region in another ion-implantation process of relatively low energy.
After the ion-implantation processes, in which an implantation mask defines the base area, the exposed semiconductor surface is thermally oxidized, forming an oxide stripe which surrounds the emitter area. Then, the portion of the oxidation mask layer is removed. Finally, the main surface is covered with an oxide layer which has contact openings to the regions to which contact is to be made by means of electrodes. As is usual with planar integrated circuits, contact is made to the regions via conducting paths which are disposed on thermally produced oxide layers and/or on a deposited oxide layer. The conducting paths contact the regions or electrodes deposited thereon through contact openings in these insulating layers.
To form the contact openings in the insulating layers, a special photolithographic etching process with a given lateral clearance from the regions to be contacted is necessary to exclude any shorting of a pn junction at the semiconductor surface.
Accordingly, the problem to be solved by the present invention is to provide a method which is compatible with the method disclosed in the above-mentioned EP-A-71 665 and permits all regions of the planar transistor to be formed so that self-alignment with their contact regions or electrodes is achieved.